Video/graphics memory system

ABSTRACT

A video/graphics memory system includes a memory device (30) having a memory core (14) and first and serial registers (16, 36). The memory device thus has a random-access port (24) for graphics data, a first serial access port (22) for image output to a display, and an auxiliary or second serial port (32) for input and output of video signal data. A single memory thus stores both video and graphics data, while the processor still has access to the random access port of the memory. Two video outputs can be provided simultaneously, or the data withdrawn through the auxiliary port can be subject to processing and then written back into the memory. In alternative arrangements, instead of using triple-ported RAM, the auxiliary port is provided by the use of external multiplexing circuitry.

BACKGROUND OF THE INVENTION

This invention relates to a computer-based video/graphics memory system,namely method and apparatus.

As is well known, one form of computer memory is random access memory(RAM). This is in integrated circuit form, and may take the form ofdynamic RAM or DRAM, or static RAM or SRAM. All types of RAM have a portthrough which random accesses to the memory locations may be made.

There is a need to use memory in a video/graphics or multi-processingapplications. `Multi-media` is now becoming an important application ofcomputer systems in which video signals at standard video line and fieldrates are intermixed for display with computer-generated graphicsimages. For display and for other purposes multiple sources anddestinations of data need to have efficient and timely access to acommon memory or storage device. It may be required to have simultaneousaccess to video, graphics and processed image data.

Conventional graphics sub-systems use dual-ported VRAM (video randomaccess memory). The random access port is used by a host processor, orif present, a graphics processor, to create a graphics image by writingpixel values into a two-dimensional pixel array within the DRAM (dynamicRAM) core of the VRAM. A serial access port (SAM) is dedicated toreading out that data in raster line format, to refresh a cathode raytube (CRT) display. The two ports, namely the normal random access portand the serial access port, function independently, except duringtransfers from the serial access port to DRAM core and vice versa.

There are problems in coordinating computer graphics and video signalsin a single system. Our U.S. Pat. No. 5,027,212 describes one system foruse in combining graphics and video information on a single display.Although extremely useful, there are limits on the capabilities of thesystem described in that patent.

SUMMARY OF THE INVENTION

The present invention in its various aspects is defined in theindependent claims below, to which reference should now be made.

Various preferred embodiments are described below with reference to thedrawings. In all these embodiments a memory device is provided with arandom-access port for graphics data, a serial access port for output ofdata to a display, and an auxiliary port for video signal data. The datalocations in the memory can selectively store both graphics data andvideo data. Thus video and graphics data can be overlaid on each other.Also, a video output can be made available additional to that throughthe serial access port. Finally data can be withdrawn through theauxiliary port, stored and/or processed and re-written back into memory,possibly at a different location.

The memory device can be a triple-ported semiconductor device, or can bedual or single ported memory provided with external multiplexingcircuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention will now be described in moredetail by way of example with reference to the accompanying drawings, inwhich:

FIG. 1 is a block diagram of a conventional graphics display systemillustrating the VRAM;

FIG. 2 is a similar diagram of a first graphics/video system inaccordance with the present invention;

FIG. 3 is a block diagram illustrating a graphics accelerator which maybe used in the system;

FIG. 4 is a block diagram illustrating the use of the system formultiple video displays and printing to a videotape;

FIG. 5 is a flow diagram illustrating a software solution to a problemwith masked usage;

FIG. 6 is a block diagram illustrating components of a hardware solutionto the same problem;

FIG. 7 is a block circuit diagram of a PC expansion card on which thesystem may be mounted;

FIG. 8 is a block diagram of a memory system in accordance with a secondembodiment of the invention;

FIG. 9 illustrates the construction of the rate converting multiplier ofFIG. 8;

FIG. 10 illustrates one possible construction for the control unit ofFIG. 8;

FIG. 11 illustrates an alternative construction for the control unit ofFIG. 8;

FIG. 12 is a block diagram of a memory system in accordance with a thirdembodiment of the invention;

FIG. 13 ilustrates the construction of the arbitrating multiplexer ofFIG. 12;

FIG. 14 is a block diagram of a memory system in accordance with afourth embodiment of the invention, using SRAMs;

FIG. 15 ilustrates the construction of the arbitrating multiplexer ofFIG. 14; and

FIG. 16 is a block diagram of a memory system in accordance with a fifthembodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A typical known computer graphics and/or video input system is shown inFIG. 1. FIG. 1 shows a VRAM (video random access memory) memory 10coupled to a host processor or graphics processor 12 through the VRAMrandom access port 24. The serial access port 22 provides a digital R,G, B output through digital-to-analog converters 18 to produce an RGBvideo output. The VRAM memory 10 also receives clock signals from avideo clock generator 20. The VRAM memory 10 contains a DRAM (dynamicrandom access memory) core 14 which provides output to a serial outputregister 16 the contents of which are read serially out through theserial access port 22.

In use, the VRAM 10 stores the computer graphics information generatedby the host or graphics processor 12 via the random access port 24.Transfer cycles are used to transfer information from the DRAM core 14to 512×4 bit serial registers 16 which typically hold up to a line ofscreen display information. The video output system will then clock datain response to the clock generator 20 serially out of the serial port 22to feed to video digital-to-analogue converters (DACs) 18. The wholebandwidth or capacity of the serial port 22 is used in displaying, ie.outputting, video.

FIRST EMBODIMENT

Basic System

The first embodiment which will now be described, and which isillustrated FIGS. 2 to 7 of the drawings, makes use of a triple-portedDRAM type number MT43C4257 or MT43C4258 made by Micron Technology Inc.,Boise, Id., USA. This DRAM has one random access port, and two identicalbidirectional serial access ports referenced SAM A and SAM B. By use ofsuch a memory, it is possible to produce an accelerated 24-bithigh-resolution graphics system which can accept video input and providevideo output, and which uses the random access port SAM Aconventionally, but uses SAM B in ways not hitherto proposed.

In the above-mentioned integrated circuit, each SAM port is four bitswide. By using a conventional pixel-interleaved memory organization; a96-bit wide bus can be provided on SAM A and a 28-bit wide bus on SAM B.The SAM B bus is divided into a 24-bit pixel bus, and a 4-bit ancillarybus. The 24 bits provide 8 bits of definition for each of three colourcomponents RGB of a colour display.

A block diagram of a first video input system embodying the invention isshown in FIG. 2. The circuit uses a triple-ported dynamic random accessmemory (TPR) 30 instead of the circuit 10 of FIG. 1. In addition to theserial port 22, this includes a second or auxiliary serial port 32 and asecond serial register 36. The second register 36 can receive data froma digital decoder 34, and the second port can be independently clockedby a clock control circuit 38. Thus there are two independentasynchronous bidirectional serial access ports in addition to theconventional RAM port 24. The circuit is preferably an integratedcircuit No. MT43C4257 from Micron Technology Inc., Boise, Id., USA.

The video output DAC 18 and clock generation 20 is entirely conventionalas is the graphics/host processor 12. In normal operation the processor12 accesses the DRAM core 14 to write graphics data and to performtransfer operations between the core 14, and serial register A (16).Serial Port B (32) is therefore freely available for video input.

The video decoder system 34 is of itself conventional and converts anincoming video data stream to a digital format (or alternatively anydigital data stream e.g. decompressed digital video data from a disc maybe used). This digital data is clocked into the serial register B of theTPR 30 under the control of the clock logic 38. This is entirelyindependent of the host processor 12 and does not interfere with thenormal graphics operations or digital video output.

When the required amount of data has been loaded into the shift register36, the address logic will request a bus cycle and perform a transfercycle to transfer the register B contents to the DRAM core 14 under thecontrol of video address generator 39. This is the only incursion on thegraphics processor bandwidth through random access port 24. Once in thecore, the input video data is indistinguishable from data written by thegraphics processor 12, and will be displayed as part of the normalgraphics display.

For a color picture there will normally be six TPRs each of which holds4 bits of data i.e. half a monochrome frame. Two are required for eachcolor.

Inlaying Graphics with Video

The TPRs have 512 mask bits per serial register i.e. one per 4 bit cell.The concept of a mask plane is well-known in graphics applications. Inthis case a single line of mask bits is provided for each pixel of aline of the image when stored in the serial register 16 or 36. When thecontents of the serial register is transferred back into the DRAM core14, the mask bit for each cell is first checked. If it is not set thenthe cell data overwrites the data in the DRAM core. If it is set, thenthe write operation is masked and the DRAM core cell data is notaltered. Hence the mask bit controls whether video or core data isstored in the core on a pixel-by-pixel basis. The mask data bit iswritten into the serial register together with the video data stream.

The mask bits can be generated in various ways depending upon the shapeof the video window to be displayed; however the ability to control themask bit on a pixel-by-pixel basis enables an arbitrary mix of video orcomputer graphics information to be stored.

One possible way to generate the mask is to provide an additionalbit-plane in the display memory by means of an additional TPR. The hostprocessor 12 writes mask data into this plane on an arbitrary basis. Thevideo address generator 39 can then transfer this data from the coreinto serial register B. The TPR containing that data is then set, sothat the serial register is in output mode, but the register B ports onthe other TPRs containing normal video are set to input mode. The maskbits are then read out of the mask plane TPR and are written along withthe video data to the appropriate B ports of the video TPRs. The maskdata should be read out of one TPR at the same time as (or at most oneclock earlier than) the corresponding data is being written into theserial register B on the other TPRs.

When the video data is transferred to the DRAM core 14 the mask bitswill ensure that video only overwrites data that was not masked, givingan arbitrary mix of video and computer-generated data. In this way inputvideo can be inlaid into a graphics image.

Windowing with Full Motion Video

It is possible to input a full motion video source into a window in thegraphics image. The digitized video is stored in and displayed from thesingle-buffered RGB graphics planes of the store.

The limitations of this approach when implemented with conventional VRAMare that the video data, which has to be input through the random accessport 24, reduces the available graphics bandwidth, and that graphicsdata cannot be overlaid onto moving video. This typically causesproblems in a graphics user interface (GUI) environment when the cursor,other windows or pull-down menus fall inside the video window.

In the present system a video input circuit (not shown) can convertbaseband analogue video from an external source into 24-bit RGB pixelsat standard line rate; this digital video stream is then written intothe graphics store through the serial register B or SAM B. Bycontrolling the tap addresses and SAM-to-core transfers appropriately,using the principles described above, the video data can overwrite thegraphics data in any desired window on the screen, without interferingwith the display refresh or reducing the graphics drawing speed. The useof the SAM port 32 for video input means that the random access port 24is fully available for graphics drawing operations, and the overhead onboth the host processor 12 and the system bus is very low.

In order that graphics data can be overlaid on full motion video,without being overwritten, a one-bit mask or key plane is defined in thepixel array which is updated as the graphics is redrawn to show wherethe video is allowed to overwrite the graphics. This key plane is usedin the following way: as-each row of video is written into the SAM pixelport, the corresponding row of the key plane is read out of the SAMancilliary port and written back into the mask register which isassociated with the pixel port. When the SAM-to-core transfer for thatrow takes place, the mask register enables writes only to those pixelswhich were `video enabled` in the key plane.

Position and Size of Image

The size and position and shape of the video image can be controlled byusing different clocks to clock data into the TPR serial port from thoseused to read data from the digital decoder. For example, if the serialregister 36 is clocked twice as fast as the data stream, then the imageclock into the TPR will be expanded (amplified) by a factor of 2. Byarbitrarily varying the clock rates and by use of appropriate buffers,the video image can be changed by any arbitrary value in the Xdirection.

Changes in the Y direction can either be performed by having aretransmittable line store or more easily by writing the contents of theserial register to more than one location in the DRAM core. For examplea ×2 (times two) amplify in Y can be performed by writing one line ofvideo data to the serial register 36 and transferring the same data totwo consecutive line locations in the TPR 30. This can be extended toany arbitrary Y change.

For both X and Y size changes non-integer changes can be achieved byvarying the rate at which pixels are replicated across the screen. Forexample if the first pixel (and line) is repeated twice, the secondthree times, the fourth twice etc., a zoom factor of 2.5 can beobtained.

The image can also be scrolled relative to the screen data withoutactually moving any data. The start position of the image is determinedby a "tap pointer" internal to a TPR. This determines where the serialregister will start accepting data when being written to. If it pointsto pixel 0 the video image will be written to pixel 0 corresponding to(for example) the left hand side of the screen display. By setting thetap pointer differently (e.g. 256) the video image will appear to havebeen scrolled to start at the centre of the screen. This control can bedone either by the host/graphics processor 12 or by a separatecontroller (not shown) that steals cycles from the host/graphicsprocessor. A similar effect is achieved in Y by changing where theserial register 36 is transferred to within the DRAM core 14.

Special effects can be achieved by mixing these two functions. Forexample a shear in X can be achieved by incrementing the tap pointer byan arbitrary amount on each successive line. By changing theamplification factor across a line the image could appear to be warpedor even wrapped round a cylinder.

All these effects are possible without actually moving the data around.

Graphics Acceleration

FIG. 3 shows an arrangement to provide fast copying and so-called"bit-blitting" of graphics information. A RAM 40, typically SRAM, isconnected to the serial register 36. A line of data is transferred intothe serial register 36 from the core 14 and then read out into theexternal RAM 40. The serial register 36 is then configured so that thetap pointer points to a different screen location. The line of data isthen read out of the RAM 40 and written back into the serial register36, but at a different tap pointer. The register contents are thentransferred back into the core 14, but at a different line address.Hence the data will appear to have been moved around the screen in bothx and y directions. By applying the same technique to each line in ascreen area, an arbitrary copy of a data can be achieved. Appropriateaddressing of RAM 40 is provided by an address generator 42, and a coreand tap address generator 44 is connected to the host processor bus andthe clock control 38. In actual fact the address generator 44 may beprovided by the host processor 12.

Subject to suitable modification of the TPR 30, movement could beachieved by writing from the core into the on-chip serial register 36and back to a different place in the core without the need to write tothe external RAM 40.

Special effects are also possible by reading data from the RAM 40 inarbitrary sequences. Amplifying and zooming of an area can be performedby reading the same data out of the SRAM 40 several times and/or atdifferent rates from the rate at which data is written into the serialregister. A zoom can be achieved by reading every pixel from the SRAM 40but writing it several times to consecutive serial register locations.An "Amplify by 4" can be achieved for example by reading every fourthpixel from the SRAM 40 and writing that same pixel to four consecutivelocations in the serial register 36. Shearing in X can also be achieved,as can some warping or similar effects. Image reversal is achieved bywriting data into the SRAM 40 in a (say) ascending address order andwriting it out in (say) descending order. Two lines can be read out ofstore sequentially and logical operations conducted on them to generatea line to be written back, e.g. in a merge.

In general, by making use of the logical operations associated in theTPR with the serial register, it is possible to provide full emulationof bit-blitting operations, with arbitrary logic and two or threeoperands. The resultant of the logic operations appears an the graphicsdisplay.

Multiple Video Displays

FIG. 4 shows a system enabling two separate screen displays 50,52 to beshown from the same area of memory 14. Serial register A and associatedlogic is entirely conventional. However, since serial register B istotally independent of register A, it can be used to generate acompletely different screen display from that from port A. For thispurpose there is an additional DAC 54, and the register 36 is clocked bya video clock generator 56.

In particular a rectangular subsection of the display generated fromport A could be configured to be a complete display on port B. Forexample, port A might be displaying an application that used manydifferent windows on screen for control information etc. at 1152×900resolution. The final output of that application might be contained anddisplayed within, say, a VGA sized area of 640×480 pixels. The wholescreen display would be displayed via port A for use by the operator,whilst port B would be set up to display only the 640×480 area on acompletely separate display system without any distracting controlinformation.

In another arrangement, port A may operate at 70 Hz for a standardgraphics display and port B operate at 50 Hz. The independent nature ofthe ports means that neither one of the displays has to have its qualitysacrificed in deference to the other.

Again it is seen that the graphics and video are mixed in the storearea. By doing this, rather than combining them after the store as inour U.S. Pat. No. 5,027,212, the danger of `frame dropping` is avoided.Frame dropping can arise if, say, an input at 50 Hz frame rate isconverted to 60 Hz or 70 Hz for display, and the resultant signal thenconverted back to 50 Hz for other purposes. Occasional frames can beomitted completely. By independently outputting the signals at twodifferent rates, and synchronising the output 50 Hz signal with theinput 50 Hz signal, the danger is avoided.

Video Rate Output

The SAM B port can be used to output RGB data from the graphics store atan average rate suitable for encoding into standard line rate basebandvideo. The region to be output is controlled by specifying appropriaterow and column addresses for the core-to-SAM transfers. This occursindependently from the high resolution graphics raster output from SAMA.

In this system, digital video data can be sampled at between 12 and 15MHz, dependent on the video system in use. This data rate uses less thanhalf of the bandwidth of the pixel-wide SAM B port. It is thereforepossible concurrently to input and output video-rate data through thesame SAM port. In fact, the logistics of input to and output fromdifferent regions in the graphics store through a single bidirectionalport mean that substantial blocks of pixels, typically one whole line,must be transferred in each direction alternately, so rate buffering isneeded to utilise the bus bandwidth effectively. If the video input andvideo output are the same TV standard and are synchronised, then theminimum buffer size required is just over half a line for eachdirection.

For simplicity, the above description assumes a one-to-one mappingbetween video pixels and graphics pixels. A PAL frame of 768 by 576pixels would occupy a window of up to 768 by 576 pixels in a graphicsdisplay area of, for example, 1024 by 768 or 1152 by 900 pixels. Areduced window size can be obtained by cropping the video using thevideo masking feature described above. The versatility of videoinput/output can be extended by scaling the video image in X and Ybefore it is written to the SAM port. The window does not then need tobe the same size as the video image.

Print To Tape Option

In particular the area chosen can be read out of the TPRs and outputstraight into a digital encoder and converted to an appropriate formatfor outputting straight to a videotape or similar storage or displaydevice. Hence no external unit would be required for displaying all orpart of the display in two different formats simultaneously or recordingall or part (e.g. just the required application window) direct tovideotape. In particular, there is no intermediate conversion of thesignal into analogue form.

To generate the best possible image quality where the required area isto be saved to tape, the data can be read out at the best possible rateto convert directly to the destination format without generating anyunwanted artefacts. This is possible because the port B data read out iscompletely independent of port A display. For example, NTSC requires640×480 at 30 frames (pictures) per second interlaced which, whilst notbeing a computer graphics display standard, could easily be generateddirectly from port B, such as by a digital encoder 58.

Other Applications

Other functions can be acheived as indicated in the following outlines:

(i) Scrolling rectangular areas: The TPR mask register is set up toprovide a rectangular mask area corresponding to the area to be scrolledvertically (up or down). The whole of a display line containing somepart of the area to be scrolled is transferred into register B. A maskedtransfer of the register is then performed to the destination line incore memory. The write operation only takes place to the unmasked areacorresponding to the data required to be scrolled.

(ii) Pattern Fills: To fill a rectangular area of memory quickly with anirregular pattern can be achieved by using part of the (non-visible) TPRmemory as a dedicated store for the pattern. Typically this is repeatedover several display lines on the screen proper when written to an areato be filled. The mask register is set up to enable writes only to thearea to be pattern-filled. A line of the pattern is read from thestorage area into the serial register B, and then transferred by amasked write operation to the appropriate screen area. If the pattern isidentical for every line further transfers take place to write theentire area. Where the pattern repeats every n lines the first patternline is written to every n'th screen line as required. The next patternline is then transferred to the serial register and written (again underthe mask) to every (n+1) the line. Patterns can alternatively be storedin the SRAM 40 in the accelerator (FIG. 3) and downloaded as required,or even generated by the host processor and written to the TPRs via theDRAM port.

(iii) Image Rotation: Rotations can be performed by shearing in Xfollowed by a shear in Y. The accelerator of FIG. 3 can be used toperform an X shear. To perform a Y shear requires successive scrolls ofnarrow parts of the image using the algorithm outlined above.

(iv) Video Image Reversal: In teleconferencing it is helpful if thevideo image can be displayed on the screen in reversed format (left toright). This can be achieved during video input by placing a buffer linestore between the digital decoder 34 and the TPR port B. Data is storedin the buffer line store in the usual left to right fashion from theincoming video stream. Data can then be read out of this store inreverse order and written into the display in the reversed format.

General Display of Data

The use of the TPR 30 and the second serial port 32 makes it very easyto display any sort of data mixed with graphics. Digital video may be aspecific example. However in general there are many sorts of processingsystems where the architecture of the memory system is tailoredspecifically to the sort of algorithms being performed. This is notusually the same architecture as is required for a display system. Hencedata generated and stored in a special-purpose memory array must be readfrom that memory, modified and then written into the normal displaymemory. These operations take processing power and involve loss ofmemory bandwidth of both the special purpose processing systems and ofthe host graphics system. In general, real time update of generated datais very difficult.

The system architecture described removes the bandwidth loss on thegraphics system, that is to say the loss of throughput capacity throughthe random access port 24 that would otherwise occur. However by usingadditional VRAMs (or TPRs or other dual ported RAM) instead of normalDRAMs within the special purpose processor's memory, data can be readdirectly from that memory and written directly into the TPRs fordisplay. Hence the only overhead on the special purpose processor is theoccasional transfer cycle (similar to refresh).

A possible extension is to provide a direct link between the TPRs andsay a disk or other serial data generating device through the secondserial access port. This link can be bidirectional. For example a diskcan provide source data (graphics or otherwise) which can be writtendirectly to the screen without any system overhead. The reverse can alsohappen where the host processor can generate graphics images (or anyother sort of data) which can be written directly to a disk or otherstorage device in real time without processor overhead.

Improper Mask Usage

One problem can arise with the system described which incorporates amask plane, in that the processor 12 may change the mask data after themask plane has been transferred into the serial register 36. Anysubsequent transfer will then use an old write mask, and the wronginformation will be placed into the core 14. This can lead to videoinput destructively overwriting graphics data. This happens when videodata is being written to the same line as graphics but because of videoline pipelining the write mask for the video is old data. Some solutionsto this problem will be described.

(i) The first solution involves checking whether any graphics writeoperation will modify the write mask in any way. This special case isthen handled by first disabling video input, then synchronising to a`safe time event`, then doing the graphics operation, and finallyre-enabling the video input. Such operations can be handled by a displaywindow manager system. The hardware needs a control bit toenable/disable video input. This will only stop/start the video at videoinput field boundaries thus giving a "clean" effect. The `safe timeevent` can then be a video input field interrupt. Synchronisation canthen involve a simple wait-for-interrupt instruction. The graphicsoperations can then proceed as normal. Finally when the graphicsoperations, with the new valid write mask (in say bit25 of the memory),have been completed, the video can be re-enabled and the hardware canbegin cleanly from a new field boundary. These steps are illustrated inthe flow chart of FIG. 5.

This approach is simple to implement and only suffers from the drawbackof temporarily halting the video input whilst graphics is actually beingwritten over inlaid video. The biggest problem then arises if a purelygraphics-based cursor is used, as any cursor movement over the videocould lead to unpleasant juddering effects. It would then be possible touse an extra four bits of graphics planes (bit25 to bit28). One bit ofthis is the write mask. This leaves three bits available for overlaygraphics, for which write masking is unnecessary. These bits can be feddirectly to a palette for creating any overlay effects as needed.

(ii) A second solution involves a hardware trap mechanism whichgenerates a "conflict" signal when graphics access is attempted into a`danger area` where video input is currently using an old write mask.The conflict signal can be used to hold the bus acknowledge signal orgenerate a bus fault, thus holding off graphics access and henceresolving the conflict.

The danger area is 256 or 512 pixels long, depending on whether splitregister write is used in the MT43C4257 or not, and most usually fallsalong a raster scan line. The trap hardware shown in FIG. 6 consists ofa range comparator 60 which looks at the current video input SAM blockwrite address and any GSP (graphics system processor) data write cyclethat is decoded into VRAM.

It is possible to use the conflict signal to hold the bus acknowledgehandshake off. This results in a totally software-transparent solution.If problems occur (like excessive refresh latency) with holding the busoff for this length of time (up to one video input line time) then busfaulting could be used. The bus fault handler should simply wait (say0.25 of a video input line time) and then just restart the cycle again.

The required hardware is closely coupled to the video input. Thecomparator range has to cover the address size of the danger area, andas such it only needs to look at 10 address lines, assuming that anexternal input from the address decoder can validate the comparison toin-VRAM access cycles only. Assuming the video input cicuitry comprisesan ASIC (application specific integrated circuit), only one extra signalline is needed to output the conflict signal. The advantage of thismethod is that it never has to freeze the video but resorts tostuttering the graphics. However, conflicts are relatively rare eventsand should not impact performance noticeably. Event resolution is aidedby writing the graphics data in the opposite direction to video inputaccess into the VRAM, as the two address streams are going in oppositedirections and hence pass through each other quickly.

(iii) A third solution also uses a hardware trap to generate the"conflict" signal to indicate the modification of an old write mask.However, in this case the conflict signal is used to change the transfermode of the video line currently being loaded. One of two actions can betaken. Either the current video line is not written, or it is written toa non-display area of memory and subsequently transferred back to thecorrect position in memory.

In the first case, of not writing the video line, then no action need betaken other than not to complete the video transfer for that line.The-net effect is that the current contents of the memory, which is thecorresponding video line of the previous frame, is frozen.

In the second case the video line is written to a pre-determinednon-display area of the memory by changing the address it is written to.The GSP can then be interrupted and subsequently take corrective actionto transfer the video line back to the correct memory area.

(iv) Finally a fourth method is to avoid the possibility of impropermask usage by ensuring that the mask plane is modified in advance of thegraphics memory rather than at the same time. This is achieved byputting a time delay between mask and graphics memory write operationsduring any processor write accesses. This is best achieved in softwareby the display window manager which would implement a delay of one videoline time whenever graphics is written into a video window.

An alternative is to implement the delay in the GSP, by writing the maskbut displaying the transfer of graphics into the main graphics memoryuntil the end of the current video line in response to video lineinterrupts.

System Block Diagram

The system can be implemented on an AT format expansion card as used inan IBM compatible personal computer. The general functional blockdiagram of the preferred system is shown in FIG. 7. The card has an ISAbus interface.

The card 100 shown has a TMS34020-32 graphics processor 102 with anassociated bus 104. A one megabyte DRAM local memory 106 is coupled tothe bus 104. The bus also terminates in an ISA bus host interface 108and edge connector and in a bus expansion connector 110. The main memorycomprises 3.5 Mbytes of video memory 112 with its appropriate control.The random access port RAP of the memory is coupled to the bus 104. Thememory 112 is constituted by TPRs, and the first serial port SAM A iscoupled to the main video DAC(s) 114, which provide a high resolutionRGB output through a connector 116. The second serial access port SAM Bof the memory 112 is connected to a video port expansion connector 118and to a blit and copy accelerator 120. The accelerator 120 is based onFIG. 3. The video port expansion connector 118 can be coupled to videoinput cards such as a digital video decoder 122 or a compressed videocard 124. These cards receive input video from the card 100. This caneither be composite video through a connector 126 or S-video (luminanceand chrominance or Y/C) through a connector 128. In each case it isapplied to the video input cards 122, 124 through an input videoexpansion port 130. Finally a VGA pass-through connector 132 receivesanalogue video that might be required to be displayed together with theoutput of the memory 112. The connector 132 is connected to a VGA (videographics adapter) DAC 134, the output of which is applied to connector116.

The 34020 processor 102 is the control and graphics processor for thecard with 1 Mbyte of local memory 106 for program storage and forholding command lists passed to it from the host processor via the ISAbus. The 34020 bus 104 is fully available on the expansion connector 110for support of multiple 34082 coprocessors, additional memory or otherprocessing engines on a daughter card.

The graphics accelerator 120 is directly under the control of the 34020,and has direct access to the video memory 112 for maximum performance.The accelerator is as illustrated in FIG. 3 and uses the additionalserial port. The copy accelerator 120 is optimised for copy functionssuch as window scrolling and moving and general bit-blitting functions,that is movement about the display with logical operations beingeffected at the same time.

The graphics accelerator 120 provides a very fast pixel copy engine thatcan sustain bit-blitting and move/scrolling operations at up to eg. 20Mpixels/sec whilst some simple pixel replication or pattern filloperations can be run at up to eg. 4 Gigapixels/sec.

The 1 megabyte of local DRAM memory 106 on the graphics system processor(GSP) bus 104 can take the form of a VRAM memory. It could also bedirectly connected to the graphics accelerator 120 by a serial link (notshown), so that it can be used as a cache store. When a window covers uppart of the image, the overlaid part can be dumped through the SAM Bport to RAM 40 in the accelerator and hence quickly and directly to the1 Mbyte DRAM memory 106 without involving the graphics processor bus104.

As illustrated 3.5 Megabytes of video display memory 112 are provided.This can take the form of a 1 Mpixel array of 4 bit overlay pixels. Thememory array drives the main video DAC 114. The video memory and DAC arefully software configurable. In conjunction with a clock synthesizer itis therefore possible to drive virtually any monitor and to generatevirually any screen format (up to 1 M displayable pixels) under softwarecontrol. The separate DAC 134 is provided to support host VGA passthrough.

Expansion for support of a video input option daughter card is providedin the form of the two connectors 126, 128 for S-video and compositevideo input and by providing the general purpose high speed (up to 120Mbytes/sec) port 118 to or from the video memory system.

Processing Video Input

Where it is required to mix an incoming video signal received at thevideo port expansion connector 118 with graphics held in the TPR memory112, it is possible to apply the video input at video rates to theaccelerator 120, to withdraw from the TPR 112 at video rates thecorresponding part of the image held in the TPR which it is intended tomix it with, do the mixing, and return the resultant to the store 112.

The alternatives would be to mix the video with the SAM A output, inwhich case the SAM A output can only run at video rates rather than themuch higher graphics standard, or to store the video in a separate framestore, which is expensive. Furthermore, the resultant of the mixing isinstantaneously viewable on the display. The system just described hassubstantial advantages over both these alternatives.

If the video input signal is an interlaced signal, the processing in thecopy accelerator 120 or in a separate processor coupled to the videoport expansion connector 118 can comprise an appropriate interpolationalgorithm so as to provide a progressively-scanned (non-interlaced orsequential) signal. The interpolation can use lines of the incomingvideo and lines held in the TPR 112, and can be movement adaptive. Thelines held in the TPR will in this case have already been through aprevious interpolation; they will not be `virgin` input lines, and theinterpolation algorithm needs to take account of this. In particularthere may need to be a threshold level at which interpolation cuts outso that there is not an unacceptable exponential decay, or blurring, onthe image. A two-line (or larger) store is required to hold lineswithdrawn from the TPR.

DRAM Port

Most if not all of the functions described above could in principle beachieved by accessing the video memory 112 not through the serial portSAM B but through the conventional VRAM random access port RAP from theGSP bus 104. In practice that is not practicable with present technologybecause the capacity of the DRAM port is insufficient at the presenttime. The second serial access port SAM B greatly facilitates theoperations and renders them a practical possibility with currenttechnology. Nevertheless many of the functions described are themselvesnew and inventive, whichever port be used to achieve them. Somealternative configurations will now be described.

SECOND EMBODIMENT

As has previously been described, the conventional graphics system usesVRAM which has a random access port for access by and to the processorand a serial access port for providing an output to the display througha digital-to-analogue conversion system. In the first embodimentdescribed above, memories with additional ports are used which allow(for example) video to be input on a third port, this being a secondserial port. This solution has substantial advantages and overcomes theperformance bottleneck which arises in the conventional VRAMconfiguration. However it requires the use of special more expensivememory devices. More generally, multi-media systems involving combinedgraphics and video in a single frame buffer, and multi-processingsystems requiring tightly-coupled and high-bandwidth communicationbetween different processors are increasingly facing these issues.

The remaining embodiments provide alternatives that emulate much if notall of the functionality of the TPRs of the first embodiment, byspecific arrangement and control of the memory devices. An efficient andcost-effective system can be provided for video/graphics andmulti-processing applications. The second embodiment uses standard VRAMvideo memories. All the systems described allow the maximum bandwidthavailable from such memory devices to be exploited.

Referring first to FIG. 8, a bank of conventional VRAM memories 210 havetheir random access ports connected via a bus to a control subsystem 218which communicates with the graphics or host processor via an interface.The serial access ports of the VRAM memories are connected to DACcircuitry 212, which outputs the R,G,B signals for display, via a rateconverting multiplexer 214. The multiplexer 214 has either an auxiliaryport 216 which is coupled to the processor through the control subsystem218, or communicates with an external auxiliary port 221, or both.

The system illustrated in FIG. 8 relies on our appreciation that in mostconventional systems the actual bandwidth available at the interfacebetween VRAMs 210 and DACs 212 is much higher than that needed by thedisplay line rate. The additional unused bandwidth is often a result ofthe mismatch that exists between the available VRAM standards and theresolution requirement of the display standards. The technique thereforeinvolves the introduction of the rate converting multiplexer 214 whichallows this bandwidth to be split up or multiplexed between that neededby the pixel rate for DACs and an auxiliary port that can be used toinput and output video graphics and processed image data.

The rate converting multiplexer receives output from the serial ports ofthe VRAMs 210 at their maximum transfer rate. In this way the timerequired to output the display data is such that a proportion of thetime is unused. During this unused time the multiplexer then connectsthe serial VRAM ports to an auxiliary port, namely either the auxiliaryport 216 or the external auxiliary port 221. When so connected data canbe transferred through the serial access port without interrupting theprocessing through the main random access ports of the VRAMs.

Depending on the organisation of the VRAM and display requirements, thedetails of the rate converting multiplexer 214 and the function providedby the control subsystem 218 will be different. FIG. 9 shows the variouscomponents of the rate converting multiplexer 214. This unit consists ofa data multiplexer 220 and rate buffers 222,224. Depending on the VRAMorganisation and display requirements, the buffer 224 on the DAC portmay or may not be needed. The rate buffers allow both DAC and auxiliaryports to run at independent rates.

The control subsystem 218 in FIG. 8 is responsible for generatingsuitable VRAM transfer cycles so that the required data is transferredfor the VRAM core memory to the serial shift registers inside the VRAM.FIG. 10 shows a block diagram of the control unit 218. When required, anaddress generator 226 within the control unit takes control of the buson the random access port 216 of the VRAM to Execute the requiredtransfer cycles. Buffers 228 are included in the bus between thehost/graphics port and the address generator 226.

An alternative way of implementing the control unit is shown in FIG. 11where a slow VRAM emulator 230 transparently steals cycles on a fastVRAM so that the host/graphics system sees a slightly slower cycle. Theaddress generator 226 uses the stolen cycles to execute the neededtransfer cycles. It should be noted that the actual bandwidth taken bythe control unit will only be a small percentage of the overallbandwidth.

THIRD EMBODIMENT

Referring to FIG. 12, which is also based on the use of standard VRAMmemories 210, in this case the serial access ports of the VRAM memoriesare coupled directly to the DAC circuitry 212, as is conventional. Inthis case an arbitrating multiplexer 236 is included between the randomaccess ports of the VRAMs and the host or graphics processor bus. Thearbitrating multiplexer has a first port 238 connected to the processorbus, and also a second, auxiliary port 240.

The system illustrated in FIG. 12 relies on the fact that in mostgraphics systems unused bandwidth also exists on the parallel signalrandom access port of VRAMs. This unused bandwidth or capacity stemsfrom the need to use multiple VRAM banks to achieve the requiredgraphics resolution and pixel rate. The technique therefore involves theintroduction of the arbitrating multiplexer 236 which allows the overallbandwidth to be split between the host/graphics processor port 238 andan auxiliary port 240. The auxiliary port can be used to input or outputvideo, graphics or processed image data The details of the arbitratingmultiplexer may vary depending on the organisation of the VRAM anddisplay requirements.

FIG. 13 shows the various components of the arbitrating multiplexer 236of FIG. 12. It includes a data multiplexer 242. A rate buffer 244 on theauxiliary port is optional and decouples the data rate on this port fromactual access into the VRAM.

The host/graphics port is handled in one of two ways. The host/graphicssystem can be put into short wait states whilst the current transactionbetween the auxiliary port rate buffer and the VRAM is taking place.This is possible in cases where the host/graphics system can respond tosuch wait requests. The alternative mode of operation consists ofinterrupting the cycle originating from/to the auxiliary portimmediately when read or write requests happen on the host/graphicsport, as illustrated by the optional hold circuit 246. The writerequests can be delayed easily and executed after the rate-buffer accessis complete.

FOURTH EMBODIMENT

The system illustrated in FIG. 14, uses a different type of memorydevice 250 namely Static Random Access Memories (SRAMs). SRAMs are muchfaster than VRAM or DRAMs and substantial bandwidth can be madeavailable by using such devices in parallel as shown in FIG. 14. Howeverthey have only one port, namely the random access port. The SRAM devicesare controlled by an arbitrating multiplexer 252 that splits the totalavailable-bandwidth between the graphics/host interface 254, auxiliaryport 256 and a third DAC output port 258 for inputting and outputtingvideo, graphics and processed images.

The principle and details of the embodiment of FIG. 14 are similar tothe third embodiment with the addition of the DAC port 258. Theconstruction of the arbitrating multiplexer is shown in FIG. 15. The DACport 258, again depending on the display and SRAM configuration, may ormay not need a rate buffer 248 as shown in FIG. 15. The operation of themultiplexer 242, host/graphics hold circuit 246 and the rate buffer 244for the auxiliary port are similar to the second method of FIGS. 12 and13.

FIFTH EMBODIMENT

Finally, a fifth embodiment is illustrated in FIG. 16. In thisembodiment VRAM 210 is used but the serial port is not connected to theDACs 212. The VRAM random access port is connected to a graphicscontroller 260, such as a VGA chip, which addresses the VRAM as thoughit were conventional DRAM without a separate serial port. The graphicscontroller is connected to the host processor interface. A videocontroller 262 can control the VRAM on the VRAM control bus. The VRAMserial port is then used as a separate video input port 264, to allowvideo to be input directly into the memory.

The random access port of the VRAM is used both for host/graphicsprocessor access and for outputting processed image data to the display.The graphics controller 260 deals with the multiplexing of host/graphicsprocessor accesses to the memory and with outputting display data. Videois written into the memory 210 by clocking into the serial port 264.Video transfers into the core memory are handled by the video controller262, which takes control of the memory control bus from the graphicscontroller and initiates a transfer cycle. This has little impact on thegraphics processing since it takes a very short time to complete. Oncecompleted, control of the VRAM memory control bus is handed back to thegraphics controller 260.

In all the embodiments described it is seen that there is a RAM memorywhich is arranged as part of a memory system. The memory system providesa random access port which is coupled to the random access port of theRAM memory. The memory system also provides a serial access port forproviding a serial output such as a graphics display. Finally, thememory system provides an auxiliary port which may be a serial port (thefirst, second and fifth embodiments) or a parallel port (third andfourth embodiments). In each case a single frame buffer is used to storeboth video and graphics data, and can be used to store processed imagedata derived from the stored image.

As compared with the system of our U.S. Pat. No. 5,027,212 only half theamount of memory is required. Furthermore host processor accessing isquicker because the processor does not have to look at two separateframe stores.

The system is nevertheless capable of inputting or outputtingfull-motion video without the need to involve the host processor in theinput or output operation. Many special features, eg. windowing andoverlaying of video and graphics, can be made available. Special effectscan be achieved by reading data out of memory, applying processing, andthen writing it back into memory.

While the separate embodiments have been described as having differentfeatures, it is to be noted that the features of the various embodimentscan be combined in ways other than those specifically described andillustrated. For example the auxiliary ports of the third and fourthembodiments could be configured as additional serial ports. Also thefeatures of FIGS. 3 and 4 can be applied to the subsequent embodiments.

We claim:
 1. In a video/graphics system comprising a processor forgenerating graphics data, a video signal port through which video dataand graphics data are transferred bidirectionally, and a display signaloutput port over which an integrated stream of video data and graphicsdata is output and a memory means, said memory means comprising:at leastone random access memory with multiple addressable data locations andhaving a random access port, said data locations in said random accessmemory being able to store selectively both graphics data from saidprocessor and video data wherein the graphics data and the video dataare written to and read from the data locations through said randomaccess port of said random access memory; a random access port, saidrandom access port of said memory means being selectively coupled tosaid random access port of said random access memory for connecting saidrandom access memory to said processor for the transfer of graphicsdata; a serial access port, said serial access port of said memory meansbeing coupled to said random access memory for connecting said randomaccess memory to said display signal output port for the transfer ofvideo data and graphics data to said display signal output port forforwarding to an external display device; an auxiliary port, saidauxiliary port of said memory means being coupled to said random accessmemory for connecting said video signal port to said random accessmemory for the transfer of video data to allow the bidirectionaltransfer of graphics data and video data to and from said random accessmemory so that the graphics data and the video data can be written toand read from individual data locations in said random access memorythrough said auxiliary port and said video signal port; and anarbitrating multiplexer coupled between said random access port of saidrandom access memory, said random access port of said memory means, andsaid auxiliary port of said memory means, whereby both said randomaccess port of said memory means and said auxiliary port of said memorymeans have time-multiplexed access to said random-access port of saidrandom access memory through said arbitrating multiplexer wherein theauxiliary port is allowed bidirectional transfer of graphics and videodata to said random access memory through said arbitrating multiplexer.2. The system claimed in claim 1, wherein said at least one randomaccess memory further includes a serial access port, and said serialaccess port of said memory means is coupled to said serial access portof said random access memory.
 3. The system claimed in claim 2, whereinsaid random access memory is a VRAM.
 4. The system claimed in claim 2,wherein said random access port of said random access memory is aparallel signal port.
 5. The system claimed in claim 1, wherein saidarbitrating multiplexer is further coupled to said serial access port ofsaid memory means whereby said random access port of said memory means,said serial access port of said memory means and said auxiliary port ofsaid memory means each have time-multiplexed access to said randomaccess port of said random access memory through said arbitratingmultiplexer.
 6. The system claimed in claim 5, wherein said randomaccess memory is a SRAM.
 7. The system claimed in claim 5, wherein saidrandom access memory is a DRAM.
 8. The system claimed in claim 1,wherein said random access port of said random access memory is aparallel signal port.
 9. The system of claim 1, wherein said arbitratingmultiplexer includes:a data multiplexer having a first end coupled toreceive data from said random access port of said memory means and saidauxiliary port of said memory means and a second end coupled to saidrandom access port of said random access memory, said data multiplexerbeing configured to connect either said random access port of saidmemory means or said auxiliary port of said memory means to said firstrandom access port; and a hold circuit connected to said random accessport of said memory means for monitoring when requests to write to saidrandom access memory are received over said random access port of saidmemory means and connected to said data multiplexer for controllingwhich of said random access port of said memory means or said auxiliaryport of said memory means is connected to said first random access port,wherein when a write request is received over said second random accessport, said hold circuit interrupts any data transfer occurring betweensaid auxiliary port and said random access port of said random accessmemory and directs said data multiplexer to connect said random accessport of said memory means to said random access port of said randomaccess memory.
 10. A video/graphics system comprising:a processor forgenerating graphics data representative of a graphics-based image; avideo signal port through which video data representative of a videoimage and graphics data are transferred bidirectionally; a memoryassembly, said memory assembly including:a random access memory havingmultiple data locations in which graphics data and video data areselectively stored, a random access port through which data areselectively written to and read from said data locations and a serialaccess port through which graphics data and video data contained in saiddata locations are read from said random access memory; a host portconnected to said processor for receiving graphics data therefrom; anauxiliary port coupled to said video signal port for receiving videodata therefrom through which the video data and graphics data areexchanged bidirectionally with the video signal port; and an arbitratingmultiplexer connected on a first side thereof to said host port and tosaid auxiliary port and on a second side thereof to said random accessport of said random access memory, said arbitrating multiplexer beingconfigured to selectively connect said host port and said auxiliary portto said random access port of said random access memory throughtime-multiplexed access so that said graphics data from said processorand video data from said video signal port can be written to said randomaccess memory and graphics data and video data can be read from saidrandom access memory to said video signal port; and an output signalport connected to said serial access port of said random access memoryfor receiving an integrated stream of graphics data and video data, saidoutput signal port functioning as a port over which the integratedstream of graphics data and video data is supplied to an externaldisplay device.
 11. The video/graphics system of claim 10, wherein saidrandom access memory is a VRAM.
 12. The video/graphics system of claim11, wherein said random access port of said random access memory is aparallel signal port.
 13. The video/graphics system of claim 10, whereinsaid random access port of said random access memory is a parallelsignal port.
 14. The video/graphics system of claim 10, wherein saidarbitrating multiplexer includes:a data multiplexer connected on oneside to said host port and to said auxiliary port and on an opposed sideto said random access port of said random access memory; and a ratebuffer connected between said auxiliary port and said data multiplexerfor decoupling the data transmission rate through the auxiliary portfrom the data transmission rate to the random access memory.
 15. Thesystem of claim 10, wherein said arbitrating multiplexer includes:a datamultiplexer having a first end coupled to receive data from said hostport and said auxiliary port and a second end coupled to said randomaccess port of said random access memory, said data multiplexer beingconfigured to connect either said host port or said auxiliary port tosaid random access port; and a hold circuit connected to said host portfor monitoring when requests to write to said random access memory arereceived over said host port and connected to said data multiplexer forcontrolling which of said host port or said auxiliary port is connectedto said random access port, wherein when a write request is receivedover said host port, said hold circuit interrupts any data transferoccurring between said auxiliary port and said random access port ofsaid random access memory and directs said data multiplexer to connectsaid host port to said random access port of said random access memory.16. The system of claim 15, wherein:said data multiplexer reads andwrites data from said random access memory at a first rate, and whendata is exchanged between said random access memory and said auxiliaryport, said the data is exchanged through a rate buffer wherein data isexchanged between said auxiliary port and said rate buffer at a secondrate that is decoupled from and less than the first rate; and said holdcircuit delays interrupting data transfers occurring between saidauxiliary port and said random access port of said random access memoryin response to write requests received by said hold circuit until afterdata in said rate buffer is accessed for the data stored in said ratebuffer.
 17. A video/graphics system comprising:a processor forgenerating graphics data representative of a graphics-based image; avideo signal port for receiving video data representative of a videoimage; a serial access port through which an integrated stream ofgraphics data and video data can be forwarded to an external displaydevice; and a memory assembly, said memory assembly including:at leastone random access memory with multiple data locations, said datalocations being used to selectively store both graphics data and videodata and a random access port through which graphics data and video dataare written to and read from the said data locations; a host port, saidhost port being connected to said processor to allow the transfer ofgraphics data from said processor to said memory assembly; an auxiliaryport, said auxiliary port being connected to said video signal port toallow the transfer of video data to said memory assembly; an arbitratingmultiplexer connected at a first end to said host port, said auxiliaryport and said serial access port and at a second end to said randomaccess port of said random access memory, said arbitrating multiplexerbeing configured to provide time-multiplexed access to said randomaccess port of said random access memory so that graphics data from saidprocessor and video data received from said video signal port can beselectively written to said data locations of said random access memoryand graphics data and video data can be read from said data locations ofsaid random access memory through said serial access port.
 18. Thevideo/graphics system of claim 17, wherein said arbitrating multiplexerincludes:a data multiplexer connected on one side to said host port, tosaid auxiliary port and to said serial access port and on an opposedside to said random access port of said random access memory; and afirst rate buffer connected between said auxiliary port and said datamultiplexer for decoupling the data transmission rate through theauxiliary port from the data transmission rate to the random accessmemory.
 19. The video/graphics system of claim 18, wherein saidarbitrating multiplexer includes a second rate buffer connected betweensaid serial access port and said data multiplexer for decoupling thedata transmission rate through the serial access port from the datatransmission rate from the random access memory.
 20. The video/graphicssystem of claim 17, wherein:said memory assembly includes a plurality ofsaid random access memories, said random access ports of said randomaccess memories being connected to said arbitrating multiplexer; aplurality of said serial access ports are provided through whichintegrated streams of graphics data and video data are forwarded to theexternal display device; and said arbitrating multiplexer is configuredto connect said random access ports of said random access memories inparallel to said serial access ports.
 21. The video/graphics system ofclaim 17, wherein said host port, said auxiliary port and saidarbitrating multiplexer are configured to allow bidirectional datatransfer between said video signal port and said data locations in saidrandom access memory.
 22. The system of claim 17, wherein saidarbitrating multiplexer includes:a data multiplexer having a first endcoupled to receive data from said host port, said auxiliary port andsaid serial access port of said memory assembly and a second end coupledto said random access port of said random access memory, said datamultiplexer being configured to connect either said host port, saidauxiliary port or said serial access port to said random access port ofsaid random access memory; and a hold circuit connected to said hostport of said memory assembly for monitoring when requests to write tosaid random access memory are received over host port and connected tosaid data multiplexer for controlling which of said host port, saidauxiliary port or said serial access port is connected to said randomaccess port of said random access memory, wherein when a write requestis received over said host port, said hold circuit interrupts any datatransfer occurring between said auxiliary port and said random accessport of said random access memory and directs said data multiplexer toconnect said host port to said random access port of said random accessmemory.
 23. The video/graphics system of claim 17, wherein said randomaccess memory is static random access memory.
 24. In a video/graphicssystem comprising a processor for generating graphics data, a videosignal port for receiving video data, and a display signal output portover which an integrated stream of video data and graphics data isoutput and a memory means, said memory means comprising:at least onerandom access memory with multiple data locations and having a firstrandom access port, said data locations in said random access memorybeing able to store selectively both graphics data from said processorand video data; a second random access port, said second random accessport being selectively coupled to said first random access port forconnecting said random access memory to said processor for the transferof graphics data; a serial access port, said serial access port of saidmemory means being coupled to said random access memory for connectingsaid random access memory to said display signal output port for thetransfer of video data and graphics data to said display signal outputport for forwarding to an external display device; an auxiliary port,said auxiliary port of said memory means being coupled to said randomaccess memory for connecting said video signal port to said randomaccess memory for the transfer of video data; and an arbitratingmultiplexer coupled between said first random access port, said secondrandom access port and said auxiliary port, whereby both said secondrandom access port and said auxiliary port have time-multiplexed accessto said first random access port of said random access memory throughsaid arbitrating multiplexer, said arbitrating multiplexer including:adata multiplexer having a first end coupled to receive data from saidsecond random access port, and from said auxiliary port and a second endcoupled to said first random access port, said data multiplexer beingconfigured to connect either said second random access port or saidauxiliary port to said first random access port; and a hold circuitconnected to said second random access port for monitoring when requeststo write to said random access memory are received over said secondrandom access port and connected to said data multiplexer forcontrolling which of said second random access port or said auxiliaryport is connected to said first random access port, wherein when a writerequest is received over said second random access port, said holdcircuit interrupts any data transfer occurring between said auxiliaryport and said first random access port and directs said data multiplexerto connect said second random access port to said first random accessport.
 25. The system of claim 24, wherein said first random access port,said auxiliary port and said data multiplexer are configured to allowbidirectional data transfer between said auxiliary port and said datalocations in said random access memory.
 26. In a video/graphics systemcomprising a processor for generating graphics data, a video signal portfor receiving video data, and a display signal output port over which anintegrated stream of video data and graphics data is output and a memorymeans, said memory means comprising:at least one random access memorywith multiple data locations and having a first random access port, saiddata locations in said random access memory being able to storeselectively both graphics data from said processor and video data; asecond random access port, said second random access port beingselectively coupled to said first random access for connecting saidrandom access memory to said processor for the transfer of graphicsdata; a serial access port, said serial access port of said memory meansbeing coupled to said random access memory for connecting said randomaccess memory to said display signal output port for the transfer ofvideo data and graphics data to said display signal output port forforwarding to an external display device; an auxiliary port, saidauxiliary port of said memory means being coupled to said random accessmemory for connecting said video signal port to said random accessmemory for the transfer of video data; and an arbitrating multiplexercoupled on one side to said first random access port and on a secondside to said second random access port, said serial access port and saidauxiliary port, whereby said second random access port, said serial portand said auxiliary port have time-multiplexed access to said firstrandom access port of said random access memory through said arbitratingmultiplexer.
 27. The system of claim 26, wherein said first randomaccess port, said auxiliary port and said data multiplexer areconfigured to allow bidirectional data transfer between said auxiliaryport and said data locations in said random access memory.
 28. Avideo/graphics system comprising:a processor for generating graphicsdata representative of a graphics-based image; a video signal port forreceiving video data representative of a video image; a memory assembly,said memory assembly including:a random access memory having multipledata locations in which graphics data and video data are selectivelystored, a random access port through which data are written to said datalocations and a serial access port through which graphics data and videodata contained in said data locations are read from said random accessmemory; a host port connected to said processor for receiving graphicsdata therefrom; an auxiliary port coupled to said video signal port forreceiving video data therefrom; and an arbitrating multiplexer connectedon a first side thereof to said host port and to said auxiliary port andon a second side thereof to said random access port of said randomaccess memory, said arbitrating multiplexer including:a data multiplexerhaving a first end coupled to receive data from said host port and fromsaid auxiliary port and a second end coupled to said random access port,said data multiplexer being configured to connect either said host portor said auxiliary port of said to said random access port; and a holdcircuit connected to said host port for monitoring when requests towrite to said random access memory are received over said host port andconnected to said data multiplexer for controlling which of said hostport or said auxiliary port is connected to said first random accessport, wherein when a write request is received over said host port, saidhold circuit interrupts any data transfer occurring between saidauxiliary port and said first random access port and directs said datamultiplexer to connect said host port to said first random access port;and an output signal port connected to said serial access port of saidrandom access memory for receiving an integrated stream of graphics dataand video data, said output signal port functioning as a port over whichthe integrated stream of graphics data and video data is supplied to anexternal display device.
 29. The system of claim 28, wherein said randomaccess port, said auxiliary port and said data multiplexer areconfigured to allow bidirectional data transfer between said auxiliaryport and said data locations in said random access memory.